The present invention relates to double data rate (DDR) static random access memory (SRAM) circuitry and more particularly to a method and apparatus for preserving data coherency in a DDR SRAM.
A DDR SRAM employs a data bus protocol in which data may be placed on a data bus twice per clock cycle (e.g., on both a rising and a falling edge of each clock cycle). More specifically, data from two addresses of the DDR SRAM may be read during a single clock cycle (i.e., a DDR read) and data may be written into two addresses of the DDR SRAM during a single clock cycle (i.e., a DDR write).
FIG. 1 is a timing diagram of a DDR write followed by a DDR read. With reference to FIG. 1, at time t0, in response to a first rising edge of a clock signal (xe2x80x9cCLK signalxe2x80x9d), the SRAM address into which data xe2x80x9cAxe2x80x9d is to be written is sent to the SRAM via a memory controller. Thereafter, at time t1, a first falling edge of the CLK signal occurs.
At time t2, the data A is placed on the data bus via the memory controller and at time t3, in response to the second rising edge of the CLK signal, the data A is written into a write buffer of the SRAM. Similarly, at time t4 the data B is placed on the data bus via the memory controller and at time t5, in response to the second falling edge of the CLK signal, the data B is written into a write buffer of the SRAM. Because of the time delay between when an address for data is sent to the SRAM and when the data is written to the SRAM, this type of SRAM is termed a xe2x80x9clate write SRAM.xe2x80x9d
In addition to writing data A into the write buffer of the SRAM on the second rising edge of the CLK signal (time t3), at time t3 the address of the first data to be read from the SRAM is sent to the SRAM via the memory controller. Thereafter, in response to the third rising edge of the CLK signal (time t6), the first data is read from the SRAM and is output by the SRAM onto the data bus at time t7. Similarly, in response to the third falling edge of the CLK signal (time t8), the second data is read from the SRAM and is output by the SRAM onto the data bus at time t9. This form of a double write followed by a read (e.g., either a single or a double read) is termed a read-following-double-write (RFDW) operation.
FIG. 1 represents a special RFDW scenario wherein the data that is written to the write buffer of the SRAM on the second falling edge of the CLK signal (e.g., data B at time t5) is the same data that is read from the SRAM on the third rising edge of the CLK signal (time t6), from an address specified at time t3. Thus, both the write operation and the read operation access the same SRAM address. Because the SRAM address for the data to be read is specified before the data has even been written to the SRAM, this form of RFDW presents special challenges. Specifically, ensuring that only the most current data (e.g., the data B written to the SRAM at time t5) is output over the data bus during the read operation (i.e., ensuring that data coherency is maintained) is difficult without sacrificing DDR SRAM performance (e.g., by requiring the processor controlling the SRAM to maintain data coherency, by requiring a full clock cycle between a data write and a data read operation and/or by accepting glitched bus transitions).
Accordingly, a need exists for a method and apparatus for preserving data coherency within a DDR SRAM without sacrificing SRAM performance.
To address the needs of the prior art, an inventive apparatus and method are provided that preserve data coherency in a DDR SRAM without sacrificing SRAM performance. To preserve data coherency in a DDR SRAM, the presence of a read-following-double-write (RFDW) condition is detected, and data is prevented from being output from the SRAM following detection of the RFDW condition until coherent data is available. To detect an RFDW condition, preferably a double write signal is detected during a double write operation, and the double write signal is latched. A read signal also is detected during a read operation and the latched double write signal is compared to the read signal. If both the latched double-write signal and the read signal are in a logic state that indicates that each is being performed, the RFDW condition is deemed detected. To prevent data from being pre-maturely output from the SRAM, the off chip driver circuitry of the SRAM preferably is maintained in a tri-state condition and data within a write buffer of the SRAM preferably is blocked until coherent data is available.
A circuit for preserving data coherency in DDR SRAM circuitry is provided. The circuit comprises an RFDW detector adapted to detect an RFDW condition, and a data output blocking circuit coupled to the RFDW detector and adapted to prevent data from being output by the SRAM following detection of an RFDW condition until coherent data is available. The RFDW detector preferably comprises a latch adapted to latch a double write signal and a comparator adapted to compare the latched double write signal to a read signal. The data output blocking circuit preferably comprises a gating circuit adapted to block data output by the write buffer of the SRAM until coherent data is available.
Because data output from the SRAM""s write buffer only is blocked until the data is coherent, data coherency is maintained without affecting performance. That is, data coherency and glitch-free data bus transitions are ensured without requiring the processor controlling the SRAM to maintain data coherency and without requiring a full clock cycle between a data write and a data read operation.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiments, the appended claims and the accompanying drawings.